In memory applications, a storage device may include a controller that sends a complementary pair of clock signals to a memory die in order to read data from the memory die and/or write data to the memory die. For read operations, in response to the clock signals, the memory die may align data pulses of data signals to the edges of the clock signals and send the aligned data signals along with clocks signals back to the controller. The controller may then process the data signals using the clock signals. For write operations, in response to the clock signals, the memory die may sample voltage levels of data pulses of data signals carrying data that the controller wants programmed into memory cells of the memory die.
Typically, the clocks signals have a 50% duty cycle. In an ideal situation, the controller generates the clock signals with the 50% duty cycle, and the duty cycle remains at 50% throughout the read process. That is, the memory die retrieving the data for the controller receives the clock signals with the 50% duty cycle, maintains the duty cycle at 50% while aligning the data, and transmits the clocks signals with a 50% duty cycle back to the controller.
However, in actual implementation, due to process-voltage-temperature (PVT) variations and silicon interface impact between the controller and the memory die, the controller and the memory die may not receive clock signals with a 50% duty cycle, leading to sampling errors. As such, ways to implement duty cycle correction schemes that move the duty cycle closer to 50% are desirable.